An Architectural Leakage Power Simulator for VHDL Structural Datapaths

We present a fast RTL leakage power simulator for datapaths described hierarchically in VHDL. Only the leafcells such as full adder, NAND gate etc., are characterized for leakage power. At the bit-slice level, exhaustive characterization can be performed in reasonable time. We observed that in the transient state, the leakage power is dependent on the previous input as well. This dependence is also incorporated into the leakage model. Using the characterized bit-slice cell library and a given set of inputs, the total leakage energy dissipated in a given datapath is estimated. Compared to HSPICE estimates, the average percentage error for three datapath-intensive designs is 1.38%. The estimation times are reduced by 4-5 orders of magnitude.